1. Field of the Invention
The present invention relates to output circuits, and more particularly, to improvement of a data output circuit used in a semiconductor memory device.
2. Description of the Background Art
FIG. 86 is a block diagram schematically showing an entire structure of a general dynamic semiconductor memory device. Referring to FIG. 86, the dynamic semiconductor memory device includes a memory cell array 900 in which dynamic type memory cells MC are arranged in a matrix of rows and columns. In memory cell array 900, a word line WL is provided corresponding to each row of memory cells. A pair of bit lines BL and ZBL are provided corresponding to each column of memory cells MC. A memory cell MC is provided corresponding to the crossing of one word line WL and a pair of bit lines BL and ZBL. FIG. 86 representatively shows one word line WL and a pair of bit lines BL and ZBL. Data complementary to each other appear on bit line BL and complementary bit line ZBL.
The dynamic semiconductor memory device further includes an address buffer 902 for generating internal row and column address signals RA and CA according to an externally applied address signal Ad, a row decoder 904 for decoding an internal row address signal RA from address buffer 902 to select a corresponding word line in memory cell array 900, and a column decoder 906 for decoding an internal column address signal CA from address buffer 902 to generate a column select signal for selecting a corresponding column (bit line pair) in memory cell array 900.
Address buffer 902 includes a row latch 905 activated in response to an internal row address strobe signal ZRAS for latching an applied address signal Ad and generating an internal row address signal RA, and a column latch 907 responsive to an internal column address strobe signal ZCAS for latching an applied address signal Ad and generating an internal column address signal CA.
A row address signal and a column address signal are provided to address buffer 902 in a time-division multiplexed manner. Internal row address strobe signal ZRAS is generated from RAS buffer 910 receiving an external row address strobe signal/RAS. Internal column address strobe signal ZCAS is generated from CAS buffer 912 activated in response to activation of internal row address strobe signal ZRAS and receiving an external column address strobe signal/CAS.
The dynamic semiconductor memory device further includes a sense amplifier 914 for detecting and amplifying data of a memory cell connected to a word line selected in memory cell array 900, and an IO gate 916 responsive to the column select signal from column decoder 906 for connecting a corresponding column (a bit line pair) in memory cell array 900 to an internal data bus 915. Sense amplifier 914 has its operation controlled by a clock control circuit 918 responsive to internal row address strobe signal ZRAS for generating a sense amplifier activation signal (not shown explicitly) at a predetermined timing. Clock control circuit 918 also controls the activation/inactivation of row decoder 904.
The semiconductor memory device further includes an ATD circuit 920 for detecting a change in internal column address signal CA from column latch 907 for generating an address transition detection signal φATD when the change is detected, an input/output control circuit 922 for generating a timing control signal determining data input/output timing according to internal column address strobe signal ZCAS from CAS buffer 912, an external write/read designating signal (write enable signal)/WE, and address transition detection signal φATD, an input circuit 924 responsive to a data write designating signal (not explicitly shown) from input/output control circuit 922 for transmitting internal write data according to external data D to internal data bus 915, and an output circuit 926 responsive to a data output permission signal from input/output control circuit 922 for generating and providing external readout data Q from the internal readout data appearing on internal data bus 915.
Write enable signal/WE specifies a data writing operation when attaining an L level (logical low), and a data readout operation when attaining an H level (logical high). The operation will now be described briefly.
When external row address strobe signal/RAS is pulled down to an L level, which in turn causes internal row address strobe signal ZRAS from RAS buffer 910 to attain an L level, a memory cycle is initiated. In response to internal row address strobe signal ZRAS attaining an L level, row latch 904 in address buffer 902 latches a currently applied address signal Ad to generate and provide to row decoder 904 an internal address signal RA. Clock control circuit 918 provides an activation signal to row decoder 904 according to this internal row address strobe signal ZRAS at L level. Row decoder 904 decodes internal row address signal RA to select a corresponding word line in memory cell array 900. As a result, data in a memory cell connected to the selected word line is read out on a corresponding bit line BL (or ZBL). Then, sense amplifier 914 is activated according to a sense amplifier activation signal (not explicitly shown) from clock control circuit 918, whereby the potentials on bit lines BL and ZBL are amplified differentially.
Following the fall of external row address strobe signal/RAS, external column address strobe signal/CAS attains an L level, and internal column address strobe signal ZCAS of an L level is generated from CAS buffer 912 attaining an enable state by internal row address strobe signal ZRAS of an L level. In response to internal column address strobe signal ZCAS, column latch 907 latches an applied address signal Ad to generate an internal column address signal CA. Column decoder 906 decodes this internal column address signal CA to generate a signal for selecting a column (a bit line pair) in memory cell array 900. Following the sensing and amplification of memory cell data on each bit line pair by sense amplifier 914, IO gate 916 responds to a column select signal from column decoder 906 to conduct, whereby a corresponding bit line pair is connected to internal data bus 915. Then, data writing or reading is carried out via input circuit 924 or output circuit 926.
FIG. 87 shows a structure of a 1-bit data output unit of output circuit 926. When the semiconductor memory device of FIG. 86 has a structure where multibit data such as 4 bits and 8 bits are input/output, a plurality of the input/output units of FIG. 87 are provided according to the number of bits of data.
Referring to FIG. 87, output circuit 926 includes an inverter 5 for inverting data ZDD appearing on an internal data bus line 915b, a 2-input AND gate 3 receiving an output permission signal OEM and an output of inverter 5, a 2-input AND circuit 4 receiving output permission signal OEM and internal readout data ZDD, a first output drive transistor 1 responsive to an output of AND circuit 3 for driving an output node 6 to a level of a power supply potential Vcc, and a second drive transistor 2 responsive to an output of AND circuit 4 for discharging output node 6 to the level of a ground potential GND. Drive transistors 1 and 2 are both formed of an n channel MOS (insulated gate type) transistor. Output permission signal OEM is generated according to internal column address strobe signal ZCAS from input/output control circuit 922 shown in FIG. 86 and address transition detection signal φATD. The operation of the output circuit shown in FIG. 87 will now be described with reference to the operation waveform diagram of FIG. 88.
At an elapse of a predetermined time period from the attaining of internal column address strobe signal ZCAS to L level, a signal of a logic opposite to that of data in the selected memory cell is transmitted on internal data bus line 915b. Internal data bus line 915b is precharged to the level of an intermediate potential during the standby state. FIG. 88 shows the state where a data signal of an L level appears on internal data bus line 915b. 
During the period when output permission signal OEM attains an L level, both outputs of AND circuits 3 and 4 attain an L level, and drive transistors 1 and 2 are both OFF. Thus, the high impedance state (Hi-Z) of output node 6 is maintained.
When output permission signal OEM attains an H level, AND circuits 3 and 4 are enabled. Data signal ZDD on internal data bus line 915b attains an H level and the output of inverter 5 attains an L level. Therefore, according to output permission signal OEM of an H level, the output of AND circuit 4, i.e., the potential of node N2 is pulled up to an H level, and second drive transistor 2 is turned on. Output node 6 is discharged to the level of ground potential GND via second drive transistor 2, whereby output data Q of an L level is provided.
When data signal ZDD attains an L level, the output of AND circuit 3, i.e., the potential of node N1 is pulled up to an H level in response to the rise of output permission signal OEM, whereby first drive transistor 1 is turned on. This causes output node 6 to be charged to a potential level lower than power supply potential Vcc by the threshold voltage of transistor 1. As a result, output data Q attains an H level. In general, a booster is provided to compensate for the threshold voltage loss of the output data.
Drive transistors 1 and 2 have their current driving capability set to drive a great current flow such as several mA in order to charge/discharge an external load at high speed to provide data speedily. A semiconductor memory device is sealed in a package. In this case, output node 6 is connected to a frame lead forming an output terminal via a bonding wire, as shown in FIG. 89. In FIG. 89, this bonding wire and frame lead are shown as output terminal 930. Not only parasitic capacitance C, but also parasitic inductance L are present in such a bonding wire and frame lead. A current change in parasitic inductance L generates a voltage represented by the equation of:V=−L·di/dtwhere di/dt is the time differential of a current i flowing through inductance L.
When drive transistors 1 and 2 are both turned off, output node 6 attains an high impedance state where the potential level of the previous output data Q is maintained. Therefore, when data Q of an L level is to be output after output data Q of an H level is provided, ringing occurs in output node 6 since output node 6 is discharged via drive transistor 2 having a great current driving capability, as shown in FIG. 90A.
When data Q of an H level is to be output after output data Q of an L level is provided, output node 6 is charged via drive transistor 1 having a great current driving capability. Therefore, overshooting occurs as shown in FIG. 90B since there is a great change in current in parasitic inductance L.
Also in the structure of maintaining output node 6 at an intermediate potential differing from the structure of maintaining output node 6 at a high impedance state, the output node precharged to the intermediate potential is charged/discharged according to the logic of the data to be output via drive transistor 1 having a great current driving capability. Therefore, the similar occurrence of ringing at the output node is encountered.
When ringing such as the above-described overshooting or undershooting occurs, there is a problem that data cannot be read out until the output data is stabilized, so that e the access time is increased. When the amplitude of generated undershooting is great, a great voltage is applied across the gate and drain (node terminal connected to output node 6) of output drive transistor 1, resulting in the problem that the breakdown voltage characteristic of transistor 1 is degraded. The same problem is encountered in drive transistor 2.
An approach of carrying out the drive of an output node in two stages is considered to prevent the above-described problem of ringing, as shown in FIG. 91. FIG. 91 shows the structure of only the portion associated with discharging the output node in two stages.
Referring to FIG. 91, the output circuit includes drive transistors 2a and 2b connected in parallel between output node 6 and a ground potential node. Drive transistors 2a and 2b are formed of n channel MOS transistors. The current driving capability of drive transistor 2a is set smaller than that of drive transistor 2b. This is realized by adjusting the channel length or the channel width of the transistor. The output of AND circuit 4 receiving output permission signal OEM and internal readout data signal ZDD is provided to the gate of drive transistor 2a. A delay stage 7 for delaying the signal potential on node N2 for a predetermined time and an AND circuit 8 for receiving an output of delay stage 7 and the signal potential on node N2 are provided to control the on/off of drive transistor 2b. The output of AND circuit 8 is provided to the gate of drive transistor 2b. Delay stage 7 includes an even number of inverters (four inverters in FIG. 91) to delay an applied signal for a predetermined time. The operation of the output circuit of FIG. 91 will now be described with reference to the operation waveform diagram of FIG. 92.
When internal column address strobe signal ZCAS attains an L level of an active state, a column select operation is initiated, and data of a selected memory cell is transmitted on internal data bus line 915b. When output permission signal OEM is pulled up to an H level, the potential of node N2 attains an H level, whereby drive transistor 2a is turned on. As a result, output node 6 is discharged mildly. The output of delay stage 7 still attains a low level, and the potential of node N3 is at an L level. Drive transistor 2b is still turned off.
When the output of the delay stage 7 attains an H level at an elapse of a predetermined time period, the output of AND circuit 8 is pulled up to an H level, whereby drive transistor 2b is turned on. As a result, output node 6 is discharged at a high speed. The potential of output node 6 is sufficiently lowered when drive transistor 2b is turned on. Therefore, there is almost no ringing even when output node 6 is discharged at high speed. This is because the maximum amplitude in a RLC circuit at the occurrence of damping oscillation is proportional to the voltage value where that rapid discharging is carried out.
A static column mode is a well known operation mode in a dynamic semiconductor memory device. As shown by the operation waveform diagram of FIG. 93, data is input/output in random by entering only an address signal with respect to one row of memory cells specified by a row address signal X in the static column mode.
More specifically, row address strobe signal ZRAS is first pulled down to an L level, whereby a row address signal is entered to select a word line. The data of memory cells connected to the selected word line are sensed and amplified by the sense amplifiers to be latched. Data of a corresponding column address is output by entering a column address signal Y asynchronously and maintaining the same for a predetermined time. In this static column mode, column address strobe signal ZCAS has the function of output enable, not the function of designating a column address latch, and is maintained at L level. In this static column mode, data can be output at high speed without toggling of column address strobe signal/CAS to enter a column address signal.
It is to be noted that output permission signal OEM is maintained at an H level as shown in FIG. 93 in a static column mode. Therefore, one of drive transistors 1 and 2a is turned on, and output node 6 is maintained at an H or L level. When data of an L level is to be provided following a data output of an H level, the potential amplitude of output node 6 is increased to generate ringing if the delay time of delay stage 7 is too short in such a static column mode operation. If the delay time of delay stage 7 is increased to prevent such generation of ringing, the access time will be lengthened to degrade the advantage of high speed access of the static column mode.
A delay stage is formed of an inverter. In general, a CMOS inverter of low power consumption is used as such an inverter. An MOS transistor has its driving capability determined depending upon the gate voltage. More specifically, the operating speed of the inverter is increased as the operating power supply voltage of the inverter forming the delay stage becomes higher, to result in a shorter delay time of the delay stage. Furthermore, an increase in the operating temperature causes reduction in the operating speed of the MOS transistor (due to increase in the threshold voltage and the channel resistance by generation of hot carriers). Therefore, as the operating temperature increases, the operating speed of the inverter forming the delay stage is reduced to increase the delay time of the delay stage. Such a variation in the delay time of the delay stage makes different the on-timing of drive transistor 2b shown in FIG. 91. In this case, a shorter delay time may cause drive transistor 2b to be turned on when the potential of the output node is not lowered sufficiently. Therefore, output node 6 will be discharged at high speed to result in generation of ringing. The driving capability of the output drive transistor is increased when the power supply voltage is increased or at a low operating temperature. Therefore, there is a problem that ringing occurs more easily.